MataiTech LLC Will Preview its EDA Tool, NAUET® 1.7 (newt), at the 4th International System-on-Chip Conference and Exhibit on Nov 1, 06

1 January 1970

MataiTech LLC will proudly preview the latest release of its flagship EDA product, NAUET™ 1.7 (newt) at the 4th international System-on Chip (SoC) Conference and Exhibit on November 1st, 2006 in Newport Beach, California.

MataiTech has enhanced its co-development tool, NAUET™, by including the world’s fist full featured SPIRIT IP-XACT™ editor designed to edit, validate and lint all aspects of the SPIRIT IP-XACT™ standard, including items that are not covered in the schema. NAUET™ is a must for anyone trying to make their components IP-XACT™ compliant.

“The enhanced NAUET component editor supports editing and verifying all aspects of the IP-XACT standard,” explained Aaron Baranoff, Vice President of Engineering at MataiTech, “With the new component editor any IP vendor or user can create or edit components and verify that they meet the IP-XACT standard. With NAUET™ 1.7’s Component Editor it is impossible to create a non-compliant IP block without being notified and flagged by the tool.”

NAUET™ 1.7 will now include a light weight RTOS generator. This provides a low overhead, royalty free operating system for SoC development and testing. NAUET customizes and builds a framework for each component in the SoC. This light weight RTOS is designed to simplify product development and make product development less expensive.

“With the inclusion of the RTOS framework customers can opt out of large footprint RTOS’s and use our simple and fast micro scheduler based RTOS. This is all part of MataiTech’s commitment to accelerate our customer’s design flow while reducing their risk,” explained Rob Fleck, Principal Product Marketing Manager at MataiTech.

NAUET™ is MataiTech’s 4th generation co-development tool. Compatible with major EDA tools, NAUET™ creates a parallel, synchronous design flow environment for co-development of SoC and software. It automatically links IP blocks, generates Verilog, VHDL, C, SystemC, RTOS framework, design documentation and test code. NAUET™ accelerates HDL coding and C/C++ coding to quickly allow engineers to begin application, driver and HDL development. Designs created with NAUET™ Component Editor are reusable as IP in later projects. NAUET™ Design Assembler is used to link multiple IP blocks into a single, larger design. NAUET™ is bundled with many OpenCores IP blocks so customers can quickly create an SoC right out of the box.

The upcoming NAUET™ 1.7 release provides Windows Vista 32 (x86) and 64 bit support. A scaled down “Lite” version and a Student/Teacher version will be launched coincidently with full featured version.

NAUET™ Lite is intended for IP providers and for customers not building large SoCs. It is useful for editing IP blocks or assembling small SoCs. NAUET™ Lite is equipped with all the powerful features available in the full featured version. It is only limited by the number of IP blocks that can be connected in one design.

NAUET™ Student/Teacher is targeted for Non-Commercial use as an educational tool and to help give real experience to students, teachers and hobbyists who want to build SoCs. This version is limited in terms of size of components as well as number of IP Blocks in an SoC.

About MataiTech

Located in Orange County California, MataiTech can bring designs to market faster than anybody in the industry. Our core engineering team has been using hardware/software co-simulation technology for years to help develop networking, encryption, parallel processing, multi-million gate ASICs, FPGAs and embedded operating systems for all industries.

See www.mataitech.com for additional information.

Contact www.socconference.com for information about the upcoming International SoC Conference and Exhibit in Newport Beach, CA.

Contact: Rob Fleck, MataiTech LLC., (rob@mataitech.com) (949 - 226 – 7079)

Source: pr

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